Article ID: 000086832 Content Type: Troubleshooting Last Reviewed: 12/07/2024

Why do the EMIF Traffic Generator 2.0 configuration and status registers reset to their default values when the WORM mode is enabled?

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
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Description

Due to a problem in the Quartus® Prime Pro Edition Software version 20.1, the EMIF Traffic Generator 2.0 (TG2) configuration and status registers (CSR) reset to their default values when Write Once Read Many (WORM) mode is enabled and a data mismatch is encountered.

Note that the WORM mode is disabled by default.

 

 

Resolution

This problem is fixed starting with the Quartus® Prime Pro Edition Software version 20.4.

Related Products

This article applies to 2 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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