Article ID: 000086824 Content Type: Troubleshooting Last Reviewed: 02/11/2023

Is rx_syncclock available for the Soft LVDS Intel® FPGA IP receiver with an even SERDES factor?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Soft LVDS Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The rx_syncclock is unused when the Intel® MAX® 10 FPGA Soft LVDS has an even serializer/ deserializer (SERDES) factor. Therefore, rx_syncclock is not available in the Soft LVDS Intel® FPGA IP receiver when an even SERDES factor is selected.

    Resolution

    No workaround is needed for this problem. 

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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