Article ID: 000086819 Content Type: Troubleshooting Last Reviewed: 06/10/2021

Why are unconstrained clocks reported in the Timing Analyzer Clocks report when using the Intel® Stratix® 10 DDR4 EMIF IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Unconstrained clocks may be reported in the Timing Analyzer Clocks report when the PLL reference clock is shared across multiple Intel® Stratix® 10 EMIF IPs because the PLL reference clock wire is routed to unused PLLs in the I/O column and the Fitter recognizes those as clock resources. For example, you may see a similar unconstrained clock message as shown below.

    emif_ddr4_1|emif_ddr4_1|arch|arch_inst|pll_inst|pll_inst~refclk_Duplicate_4~io48tilelvds_0/s43_0_0__ioclknet48_tile__ref_clk0.reg  ;                                      ; Base      ; Unconstrained ;

    Resolution

    You can safely ignore these unconstrained clocks because they are not used in the design.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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