Description
Due to a problem in the Intel® Quartus® Prime Pro Edition 18.0 and earlier, you may see this internal error when implementing a LVDS SERDES IP with Use external PLL option where its LVDS external ports ext_loaden and ext_fclk connect directly to top level.
Resolution
To work around the problem, connect both LVDS ext_loaden and ext_fclk to an external PLL.
This problem is scheduled to be fixed in a future release of Intel® Quartus® Prime Pro Edition software.