Article ID: 000086808 Content Type: Troubleshooting Last Reviewed: 12/28/2022

Why does the EMIF Traffic Generator 2.0 fail at higher frequencies for multi rank LRDIMM targeting the External Memory Interfaces Intel® Agilex™ FPGA IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Memory Interfaces and Controllers
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2 and earlier, the EMIF Traffic Generator 2.0 may fail at 1333MHz or higher clock frequencies for a multi rank LRDIMM targeting the External Memory Interfaces Intel® Agilex™ FPGA IP.

     

    Resolution

    If you encounter bit errors at the start or end of the burst length of 8, increase the additional bus turnaround time (as shown below) under the Controller tab in the External Memory Interfaces Intel® Agilex™ FPGA IP.

    Additional read-to-write turnaround time (same rank)

    Additional write-to-read turnaround time (same rank)

    Additional read-to-read turnaround time (different ranks)

    Additional read-to-write turnaround time (different ranks)

    Additional write-to-write turnaround time (different ranks)

    Additional write-to-read turnaround time (different ranks)

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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