Description
In the Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, the I/O timing closure flow support using a simulation-based approach for evaluating board signal integrity is not available for the Intel Agilex® 7 FPGA QDR-IV IP.
Note that this I/O timing closure flow support is available for the Intel Agilex® 7 FPGA DDR4 IP.
Resolution
The I/O timing closure flow support for the Intel Agilex ® 7 FPGA QDR-IV IP is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.