Article ID: 000086776 Content Type: Troubleshooting Last Reviewed: 12/19/2018

Do I need to follow tR and tF specification for fast passive parallel when DCLK-to-DATA ratio is larger than 1 in Intel® Arria® 10 Devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No.  There is Table 80.  FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel® Arria® 10 Devices in Intel Arria 10 Device Datasheet.  The table in version 2018.09.24. or earlier described tR or tF specification which is incorrect. There should be no tR or tF specification in the FPP Timing Parameters.

Resolution

tR and tF specification have been removed from FPP Timing Parameters since Intel Arria 10 Device Datasheet version 2018.11.29.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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