Article ID: 000086758 Content Type: Troubleshooting Last Reviewed: 03/01/2021

Why does the External Memory Interfaces Intel® FPGA IP encounter a fitter compilation error when an I/O lane does not have all 12 pins bonded out?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
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    Description

    You may encounter a fitter compilation error in the Intel® Quartus® Prime software if the External Memory Interfaces Intel Arria® 10 FPGA IP or External Memory Interfaces Intel Cyclone® 10 GX FPGA IP has a DQ group placed in an I/O lane that contains unbonded FPGA I/O pins.  

    Resolution

    To work around this problem, you need to ensure the External Memory Interfaces Intel®Arria® 10 FPGA IP or External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP DQ group is placed in an I/O lane where all 12 pins are bonded out.  

    Related Products

    This article applies to 2 products

    Intel® Cyclone® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs

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