Article ID: 000086753 Content Type: Troubleshooting Last Reviewed: 08/12/2021

Why does the EMIF Traffic Generator 2.0 become unresponsive when the burst length reaches or passes the end of the memory address space?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, you may see that the EMIF Traffic Generator 2.0 (TG2) does not assert the pass, fail, or timeout signals when the TG2 is set to sequential mode and the written address is within 127 address spaces to the end of the memory.

    For example, if the address 0xfff0 is written to with a burst length of 0x20, the TG2 will become unresponsive because this is an invalid command.

    Note: This problem does not occur when the TG2 is set to random mode or random-sequential mode because the address is generated to account for the size of the burst length.

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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