Article ID: 000086750 Content Type: Troubleshooting Last Reviewed: 02/10/2023

Is LVDS I/O standard input pin supported on the 3V I/O bank when powered by VCCPT?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, you cannot place the LVDS I/O standard input pin into 3V I/O banks even when powered by VCCPT. You will receive the following error message:
Error (14566): The Fitter cannot place <number of failed cells> periphery component(s) due to conflicts with existing constraints <failed cell summary> if you place the LVDS I/O standard into 3V I/O banks.

Resolution

There is no workaround for this problem.

Related Products

This article applies to 3 products

Intel® Cyclone® 10 GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs