Article ID: 000086746 Content Type: Troubleshooting Last Reviewed: 10/22/2018

Why do I see JIC programming failure when using the OSC_CLK_1 for Intel® Stratix® 10 devices?

Environment

  • Intel® Stand-Alone Programmer 10.23 (For Legacy Max+Plus® II Software)
  • Configuration Clock Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You will see JIC programming failure when current design is running in the FPGA is using OSC_CLK_1 as the configuration clock source AND reprogram the JIC file with a different Intel® Quartus® Prime Programmer version.

    Resolution

    1) Load the JIC file using the same Intel® Quartus® Prime Programmer version. Then, configure the Factory Default Helper Image.
    2) Erase the flash.
    3) Power cycle the board.
    4) Reprogram the JIC with a different Intel® Quartus® Prime Programmer version.

    Example: with condition design running in the FPGA is using OSC_CLK_1

    1) Failing case: 
    Load 18.0 JIC programmed using Intel® Quartus® Prime Programmer version 18.0 --> reprogram 18.0 JIC using Intel® Quartus® Prime Programmer version 18.1

    2) Passing case:
    Load 18.0 JIC programmed using Intel® Quartus® Prime Programmer version 18.0 --> reprogram Factory Default Helper Image using Intel® Quartus® Prime Programmer version 18.0 --> reprogram 18.0 JIC using Intel® Quartus® Prime Programmer version 18.0
    OR
    Load 18.0 JIC programmed using Intel® Quartus® Prime Programmer version 18.0 --> reprogram Factory Default Helper Image using Intel® Quartus® Prime Programmer version 18.0 --> Erase the flash --> Power Cycle --> reprogram JIC using Intel® Quartus® Prime Programmer version 18.1

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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