Article ID: 000086720 Content Type: Error Messages Last Reviewed: 05/23/2019

Warning (332049): Ignored create_generated_clock at .sdc: Option -phase: Invalid phase shift

Environment

  • Intel® Quartus® Prime Standard Edition
  • Soft LVDS Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Standard Edition software version 18.1 and earlier, you may see the warning message above in the fitter stage if you use the write_sdc -expand <project>.sdc command in the Intel® Timing Analyzer. This problem occurs if you have the Intel® Max® 10 soft LVDS Intel® FPGA IP in your design.

    Resolution

    To work around this problem, modify the create_generated_clock phase of <project>.sdc with the following:

    From -phase -90/1 modify to -phase [expr -90/1]

    This problem is fixed starting with the Intel® Quartus® Prime Standard Edition software version 19.1.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.