Due to a problem in the Intel® Quartus® Prime Standard Edition software version 18.1 and earlier, you may see the warning message above in the fitter stage if you use the write_sdc -expand <project>.sdc command in the Intel® Timing Analyzer. This problem occurs if you have the Intel® Max® 10 soft LVDS Intel® FPGA IP in your design.
To work around this problem, modify the create_generated_clock phase of <project>.sdc with the following:
From -phase -90/1 modify to -phase [expr -90/1]
This problem is fixed starting with the Intel® Quartus® Prime Standard Edition software version 19.1.