Article ID: 000086708 Content Type: Troubleshooting Last Reviewed: 10/03/2017

Does the Stratix 10 hard memory controller support 2T timing for the address/command bus?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Stratix® 10 hard memory controller operates at 1T timing for the address/command bus. It doesn't have the option to select 2T timing.

    Resolution

    If 2T timing for the address/command bus is required, choose the PHY-only option in the Stratix 10 EMIF IP Editor and develop your own custom controller. Note that calibration is always performed assuming 1T timing, which is safe for both 1T or 2T operations subsequently.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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