Description
After generating the PHYLite for Parallel Interfaces Intel® FPGA IP, its phase-locked loop (PLL) reference clock is a single-ended input clock with an I/O standard determined by the IP General Tab > I/O Settings > I/O standard parameter.
A differential PLL reference clock with LVDS I/O standard is also supported and is implemented by adding a QSF I/O standard constraint :
set_instance_assignment -name IO_STANDARD LVDS -to <ref_clk>
This causes the critical warning.
Resolution
You can safely ignore this critical warning.