Article ID: 000086691 Content Type: Troubleshooting Last Reviewed: 12/17/2019

Why does the output clock signal of the ALTCLKCTRL Intel® FPGA IP is stuck high in the Intel® Arria® 10 SX Devices?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime you might see for the Intel® Arria® 10 SX Devices, the ALTCLKCTRL Intel® FPGA IP output clock signal is stuck high when it's assigned to CLKCTRL_2L_G_I17 location.

    Resolution

    To work around this problem, create a dummy instance of the ALTCLKCTRL Intel® FPGA IP, and add the following assignments in the Intel® Quartus® settings file (.qsf) to preserve the dummy instance and to fix the location to CLKCTRL_2L_G_I17.

     

    set_location_assignment CLKCTRL_2L_G_I17 -to <dummy_clkctrl_instance_name>

    set_instance_assignment -name PRESERVE_FANOUT_FREE_WYSIWYG ON -to <dummy_clkctrl_instance_name>

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 SX SoC FPGA

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