Article ID: 000086689 Content Type: Troubleshooting Last Reviewed: 09/11/2020

Why do I see the hold timing violation in DCP1.2 OpenCL BSP design?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® FPGA SDK for OpenCL™ Pro Edition
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Description

You may see a small hold timing violation when you compile a DCP1.2 OpenCL BSP design.

 

Resolution

This hold timing violation does not cause any functional issue on DCP1.2 OpenCL BSP design.

This problem has been fixed in DCP 1.2.1 OpenCL BSP design. 

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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