Article ID: 000086669 Content Type: Error Messages Last Reviewed: 10/10/2018

Error (175006): There is no routing connectivity between the IOPLL and destination LVDS_CHANNEL

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this error in the Intel® Quartus® Prime Pro software when using LVDS SERDES Intel FPGA IP with Intel Stratix® 10 devices. This error is occurs when the input clock signal of the IOPLL is being sourced through the FPGA core

Resolution

To avoid this error, provide the input clock signal to the IOPLL through dedicated clock pins.   

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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