This error may be seen in Quartus® Prime Pro Edition Software during compilation of all Agilex™ device targeted design that contains the Generic Serial Flash Interface FPGA IP design with exported conduits. This is because there is an Output Enable (OE) conflict in the design pin placement. The error may be duplicated on different pins assignments if there are multiple OE conflicts being detected.
In all Agilex™ devices, there is a pin placement requirement due to the fact that the OE hardware is shared amongst x4 DQ group pins. Thus, if there are two conduits having their own respective OE signals, they should be assigned to different x4 DQ group pins to avoid OE conflicts.
Generic Serial Flash Interface FPGA IP (viewed in Technology Map Viewer)
| OE signals | Exported Conduits |
|---|---|
| dedicated_interface:data_buf[0]~0 | qspi_pins_data[0] |
| dedicated_interface:data_buf[1]~1 | qspi_pins_data[1] |
| dedicated_interface:data_buf[2]~2 | qspi_pins_data[2] qspi_pins_data[3] |
| qspi_inf_inst:oe_reg | qspi_pins_dclk qspi_pins_ncs |
To avoid this error, exported conduits with different OE signals should be established in a different x4 DQ group, whereas exported conduits with a shared OE signal are recommended to be established within the same x4 DQ group. Example using an Agilex™ device (AGFB027) is shown in the following table:
| Exported Conduits | Pin Placement | x4 DQ group (AGFB027) |
|---|---|---|
| qspi_pins_data[0] | W34 | DQ133 |
| qspi_pins_data[1] | J35 | DQ135 |
| qspi_pins_data[2] qspi_pins_data[3] | L38 W38 | DQ132 |
| qspi_pins_dclk qspi_pins_ncs | J39 C38 | DQ134 |
The information is available in Agilex™ General-Purpose I/O and LVDS SERDES User Guide and Pin-Out Files for FPGA.