Article ID: 000086659 Content Type: Troubleshooting Last Reviewed: 03/07/2022

Why is the Configuration via Protocol (CvP) periphery image configuration time exceeding the PCIe 100ms power-up-to-active time requirement?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In Intel® Quartus® Prime Pro Edition Software version 21.2, the CvP PCIe link may not be able to enumerate properly with Intel® Agilex™ F-Tile & R-Tile devices. This is because the periphery image configuration time exceeds the PCIe 100ms power-up-to-active time requirement.

    Resolution

    To work around this problem, re-enumerate the PCIe link once the FPGA is successfully configured.

    This problem is scheduled to be fixed in a future release of Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
    Intel® Agilex™ 7 FPGAs and SoC FPGAs I-Series

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