Description
In Intel® Quartus® Prime Pro Edition Software version 21.2, the CvP PCIe link may not be able to enumerate properly with Intel® Agilex™ F-Tile & R-Tile devices. This is because the periphery image configuration time exceeds the PCIe 100ms power-up-to-active time requirement.
Resolution
To work around this problem, re-enumerate the PCIe link once the FPGA is successfully configured.
This problem is scheduled to be fixed in a future release of Intel® Quartus® Prime Pro Edition Software.
