Article ID: 000086657 Content Type: Troubleshooting Last Reviewed: 12/13/2016

Why does my RAM inference fail for Stratix 10 designs?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Quartus® Prime Pro edition software, you may see that RAMs that were inferred as M20Ks in Stratix® V or Arria® 10 are not inferred in Stratix 10 for one of the following reasons:

    • Stratix 10 does not support True Dual Port (TDP) dual clock RAMs
    • Stratix 10 does not support mixed width TDP RAMs
    • Stratix 10 does not support "old data" mixed port read-during-write(RDW) behaviour for TDP RAMs
    • Stratix 10 only supports mixed width simple dual port (SDP) RAMs with ratios of 1:2 and 1:4 (1:8, 1:16 and 1:32 are not supported)

     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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