In the Quartus® Prime Pro edition software, the JTAG signals are no longer automatically constrained.
As a result of this you may experience triggering problems using the SignalTap™ II Logic Analyzer and any other tools using the JTAG interface.
Apply timing assignments, such as the examples below, to ensure correct functionality of the JTAG interface:
create_clock -name altera_reserved_tck -period 10 [get_ports altera_reserved_tck]
#cut all paths to and from altera_reserved_tck
set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]
# I/O min delays
set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tdi] -min 2
set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tms] -min 2
set_output_delay -clock altera_reserved_tck [get_ports altera_reserved_tdo] -min 3
# I/O max delays
set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tdi] -max 3
set_input_delay -clock altera_reserved_tck -clock_fall [get_ports altera_reserved_tms] -max 3
set_output_delay -clock altera_reserved_tck [get_ports altera_reserved_tdo] -max 4
Note that the values specified in the constraints above are arbitrary values. You should ensure that the values you specify match the destination hardware.
