Why is the SPT/CPB block content erased when using the Mailbox Client Intel® FPGA IP in Intel® Stratix® 10 or Intel® Agilex™ devices to execute the QSPI_ERASE command to erase and update the P1 partition / Application Image 1?

Due to problem in Intel® Quartus® Prime Pro Edition software starting from version 19.3 and above, when the start address of the P1 partition / Application Image 1 is manually assigned by the user,  the Programing File Generator tool will assign the Sub-partition table (SPT) or pointer block (CPB) contents in the same flash sector (64KB) with the P1 partition / Application Image 1.

Therefore, the content of the SPT/CPB block will be erased when using the Mailbox Client Intel® FPGA IP in Intel® Stratix® 10 or Intel® Agilex™ devices  to execute the QSPI_ERASE command to erase and update the P1 partition / Application Image 1.

To work around this, add 32KB padding to the factory image..

This problem is scheduled to be fixed in future release of Intel® Quartus® Prime Pro Edition software.