Article ID: 000086622 Content Type: Troubleshooting Last Reviewed: 04/26/2021

Why can't QSPI flash be accessed using the Mailbox Client Intel® FPGA IP in designs that include HPS?

Environment

  • Quartus® II Subscription Edition
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    Description

    In Intel® Stratix® 10 and Intel® Agilex™ devices with HPS, due to the implementation of HPS software, once the HPS is released from reset, you cannot access QSPI flash using the Mailbox Client Intel® FPGA IP.

    You will see error code 0x81 (QSPI_ALREADY_OPEN)  for QSPI_OPEN operation (Please refer to Mailbox Client Intel® FPGA IP User Guide for the details of the operation command and error codes). 

    Resolution

    This is expected behavior. In designs which include HPS, both SDM and HPS cannot access the shared QSPI flash simultaneously. 

    Related Products

    This article applies to 3 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 SX SoC FPGA

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