Article ID: 000086618 Content Type: Error Messages Last Reviewed: 03/16/2021

Warning (176441): The I/O pin < pin name > cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB).


  • Intel® Quartus® Prime Standard Edition

    Intel® Quartus® Prime Standard edition software may issue this warning message during compilation when you use LVDS receiver in an Intel® MAX® 10 device and constrain setup and hold times for the input pins in the Synopsys Design Constraint (SDC) file. This is because when a PLL is set to source synchronous or ZDB mode for LVDS designs, optimal delay chain settings are automatically used during compilation, but the setup and hold time constraints for the LVDS receiver inputs are ignored. The warning is issued to notify the user of the ignored constraints.

    Even though the setup and hold time constraints for the LVDS receiver inputs in the SDC are ignored during compilation, the Timing Analyzer uses them for timing analysis after compilation.


    You can safely ignore this Warning message.

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs



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