Critical Issue
Description
You may receive this error when you place pins surrounding 1.0 V I/O standard pins within the same bank despite meeting the total mutual inductance requirement based on mutual coupling spreadsheet for Intel® MAX® 10 FPGA device. This is a known issue due to the outdated database for both the Intel® Quartus® and the spreadsheet.
Resolution
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition software.