Critical Issue
Description
You might receive this error when you place pins surrounding 1.0 V I/O standard pins within the same bank, despite meeting the total mutual inductance requirement based on the mutual coupling spreadsheet for the MAX® 10 FPGA. This is a known problem due to the outdated database for the Quartus® Prime Software and the spreadsheet.
Resolution
This problem is fixed in the Quartus® Prime Pro Software version 22.1.