Article ID: 000086605 Content Type: Troubleshooting Last Reviewed: 08/12/2021

Critical Warning (21688): The total mutual inductance (Lm) of 1.0 V I/O < pin location > with surrounding 1.0 V I/O pins is < total mutual inductance value > nH. This is not allowed. The total mutual inductance must be less than or equal to < value

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You may receive this error when you place pins surrounding 1.0 V  I/O standard pins within the same bank despite meeting the total mutual inductance requirement based on mutual coupling spreadsheet for Intel® MAX® 10 FPGA device. This is a known issue due to the outdated database for both the Intel® Quartus® and the spreadsheet. 

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition software.

     

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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