Article ID: 000086548 Content Type: Troubleshooting Last Reviewed: 03/27/2018

Why Arria 10 SoC HPS EMAC timestamp is not running after timestamp interface is exported to FPGA?


  • Hard Processor System Intel® Arria® 10 FPGA IP

    Arria 10 SoC devices may encounter the following problems when HPS EMAC timestamp interface is exported to FPGA fabric:

    1.      Timestamp counter is not running

    2.      PTP reference CLK mux does not source from FPGA CLK



    EMAC PTP reset bit is required to be released prior to switching the clock mux from HPS Clock Manager to FPGA clock source.

    Arria 10 Hard Processor Technical Reference Manual is schedule to be updated in future release for below chapter:

    In the section Ethernet MAC Programming Model -> EMAC FPGA Interface Initialization:

    1. After the HPS is released from cold or warm reset, reset the Ethernet Controller module by setting the appropriate emac* bit in the per0modrst register in the Reset Manager:
      • emac reset bits [2:0] – reset for EMAC0/1/2 port
      • emacptp reset bit [22] – reset for EMAC PTP interface, only required when PTP timestamp interface is enabled.
    2. Configure the EMAC Controller clock to 250 MHz by programming the appropriate registers in the Clock Manager.
    3. Bring the Ethernet PHY out of reset to verify that there are RX PHY clocks.
    4. If the PTP clock source is from the FPGA,
      • release per0modrest.emacptp bit from reset then only configure emac_global register to select f2s_ptp_ref_clk from the FPGA fabric.
      • ensure that the FPGA f2s_ptp_ref_clk is active.


    Related Products

    This article applies to 1 products

    Intel® Arria® 10 SX SoC FPGA



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