Article ID: 000086486 Content Type: Troubleshooting Last Reviewed: 12/01/2014

What can I do if the ALTGX_RECONFIG IP reconfig_busy signal is stuck high on Arria II, Cyclone IV, or Stratix IV transceiver devices?

Environment

  • Stratix® IV GX FPGA
  • Stratix® IV GT FPGA
  • Arria® II GZ FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    If the transceiver ALTGX_RECONFIG IP reconfig_busy signal is stuck high on Arria® II, Cyclone® IV, or Stratix® IV transceiver devices, you can enable and assert the ALTGX_RECONFIG IP reconfig_reset signal.

    Resolution

    You can enable the reconfig_reset signal on the ALTGX_RECONFIG IP using the instructions below.

    1. Open the ALTGX_RECONFIG IP.
    2. Enable \'Channel reconfiguration\'.
    3. Enable "Use \'reconfig_reset\'" in the \'Channel and TX PLL reconfiguration\' page.
    4. Press \'Finish\' to generate the IP.
    5. Connect a synchronous reset signal to the reconfig_reset port.

    The following rules apply to the reconfig_reset signal:

    • The reconfig_reset signal must be synchronous to the reconfig_clk clock.
    • The reconfig_reset signal must be high when the device enters user mode.
    • The reconfig_reset signal must be asserted for at least one reconfig_clk clock cycle.

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