Nios® II/f Processor may erroneously clear Processor Interrupt-Enable bit

Due to a problem in the Nios® II Processor, when implemented as a Nios II/f with a data tightly-coupled memory (DTCM), it is possible that a specific sequence of instructions may cause the Processor Interrupt Enable (PIE) bit in the status register to be erroneously cleared before entering the interrupt handler.  This may cause software to behave in an unexpected fashion.  An example of a sequence of instructions that would cause this behavior is as follows:

1:  ldw r17, 0(r16)     // fetch pointer to DTCM from some other, higher latency memory

2:  stw r2,  8(r19)     // store to DTCM

3:  ldw r2,  0(r17)     // reference previous pointer

If an interrupt occurs during the stall for instruction 1, the Nios processor may also complete instruction 2 and erroneously clear status.PIE.

This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 18.1.1