Article ID: 000086474 Content Type: Troubleshooting Last Reviewed: 05/04/2018

Why does Stratix 10 SoC fail to complete JIC flash file programming when using combined FPGA and HPS JTAG?


  • Intel® Quartus® Prime Pro Edition
  • Configuration Clock Intel® Stratix® 10 FPGA IP

    Critical Issue


    In the Intel® Quartus® Prime Pro software version 18.0, the Quartus Prime Programmer tool may crash when attempting to perform JIC file programming, if the Intel Stratix® 10 SoC device is already configured with the combined FPGA and HPS JTAG option. This is because the FPGA is initially the second device in the JTAG chain (after the HPS) - however once the SFL helper image is programmed, the HPS is removed and the FPGA is now the first device in the JTAG chain.

    The discrepancy in JTAG device numbering causes the Quartus Programmer tool to crash as it is expecting the FPGA device to remain at the same location in the JTAG chain during the entire process.  

    This issue does not impact you if:

    1. The Intel® Stratix® 10 SoC device remains unconfigured before the start of JIC file programming
    2. The Intel Stratix 10 SoC HPS JTAG is using the HPS dedicated I/O pins and does not share the same JTAG chain with FPGA.

    Use one of the following workarounds in order to perform flash programming on the board:

    1. Power up the board with MSEL[2:0] set to 111 (JTAG). In this way, the device will remain unconfigured prior to JIC file programming, and the JTAG chain will contain only one device (FPGA). Once the Quartus Prime Programmer tool has completed the JIC file programming, you can set the MSEL[2:0] back to 100 in order for the device to boot automatically from QSPI on the next power cycle.
    2. Externally pull nCONFIG to low when powering up the board to prevent device from configuring using QSPI. Initiate JIC programming using JTAG - once SFL helper image have been programmed, you can release the nCONFIG pin. 
    3. Use the software running in the HPS (for example, U-boot) to program the QSPI device. This method uses the Raw Programming Data (.rpd) file format instead of a JIC file. Refer to the Intel Stratix 10 Configuration User Guide for steps to generate the .rpd programming file.  

    This problem will be fixed in future version of the Intel Quartus Prime Pro software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 SX SoC FPGA