Although the Technical Reference Manual (TRM) for SoC devices contains description how QSPI controller operate in so called indirect mode, there was a confusion how the indaddrtrig register should be set.
"This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address 15, then the AHB request will be completed by fetching data from the Indirect Controllers SRAM."
Documentation will be updated with information in Workaround/Fix section.
Following text is going to replace existing description in updated documentation.
"This register is used by the QSPI controller to discern whether incoming memory accesses on the QSPI AHB memory window are meant to access the SRAM FIFO or to be interpreted as direct access requests. When the incoming access is between indaddrtrig .. indaddrtrig 15 the access is directed towards SRAM FIFO, otherwise it is interpreted as a direct access request. Note that it does not matter which address in the indaddrtrig .. indaddrtrig 15 interval is accessed, any access is treated the same and will be directed to SRAM FIFO. When direct mode is not used, the recommended procedure is to leave indaddrtrig as 0, and use the base of the AHB memory window to access the SRAM FIFO."