Article ID: 000086459 Content Type: Troubleshooting Last Reviewed: 06/30/2021

Why does the Intel® Agilex™ HPS inadvertently enters a Cold Reset (HPS_COLD_nRESET pin)?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    According to the Intel® Agilex™ Device Data Sheet, the minimum reset pulse width for the HPS_COLD_nRESET signal is 3 msec (Trst0).  If a pulse width of less than 3 msec occurs on this pin, an unintentional reset may occur.  The HPS system may inadvertently detect pulses as short as approximately 0.3 msec in width.

    Resolution

    To work around this issue, implement an external hardware debounce circuitry that will hold the HPS_COLD_nRESET signal asserted for a minimum of 3 msec.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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