A common solution to simplifying address decoding is to put peripherals attached to the data master of a Nios II processor behind an Avalon Pipeline Bridge, and sometimes this can include some memory IP, such as an On-Chip RAM. However, if the memory is expected to contain Nios II program code, it should be connected in the same method to the Nios II instruction master as it is connected to the data master. In other words, a memory should not be directly connected to a Nios II instruction master and also simultaneously connected to the data master through a pipeline bridge; it should be directly connected to both data and instruction masters. It is likely that designs in which memories are not connected similarly to both masters will face challenges during debug; and such designs that also feature flash memory interfaces will cause the Nios II Flash Programmer to fail to program.
Memories that contain Nios II Program code should be connected directly to the data and instruction masters.