Article ID: 000086454 Content Type: Troubleshooting Last Reviewed: 06/05/2017

What modifications are needed to use the MT25QU02GCBB8E12-0SIT QSPI device in u-boot-socfpga?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    To add support for the  MT25QU02GCBB8E12-0SIT  QSPI device in u-boot-socfpga for Arria 10 in the SoC EDS 17.0, make the following changes to uboot-socfpga/drivers/mtd/spi/sf_params.c

     

     

    Resolution

    Edit the file uboot-socfpga/drivers/mtd/spi/sf_params.c in a text editor, and add the device (addition shown in bold): 

    #ifdef CONFIG_SPI_FLASH_STMICRO           /* STMICRO */

          {"M25P10",     0x202011, 0x0, 32 * 1024,     4, 0,                  0},

          {"M25P20",     0x202012, 0x0,       64 * 1024,     4, 0,                  0},

          {"M25P40",     0x202013, 0x0,       64 * 1024,     8, 0,                  0},

          {"M25P80",     0x202014, 0x0,       64 * 1024,    16, 0,                  0},

          {"M25P16",     0x202015, 0x0,       64 * 1024,    32, 0,                  0},

          {"M25PE16",    0x208015, 0x1000,    64 * 1024,    32, 0,                  0},

          {"M25PX16",    0x207115, 0x1000,    64 * 1024,    32, RD_EXTN,                  0},

          {"M25P32",     0x202016, 0x0,       64 * 1024,    64, 0,                  0},

          {"M25P64",     0x202017, 0x0,       64 * 1024,   128, 0,                  0},

          {"M25P128",    0x202018, 0x0,      256 * 1024,    64, 0,                  0},

          {"M25PX64",    0x207117, 0x0,       64 * 1024,   128, 0,              SECT_4K},

          {"N25Q32",     0x20ba16, 0x0,       64 * 1024,    64, RD_FULL,       WR_QPP | SECT_4K},

          {"N25Q32A",    0x20bb16, 0x0,       64 * 1024,    64, RD_FULL,       WR_QPP | SECT_4K},

          {"N25Q64",     0x20ba17, 0x0,       64 * 1024,   128, RD_FULL,       WR_QPP | SECT_4K},

          {"N25Q64A",    0x20bb17, 0x0,       64 * 1024,   128, RD_FULL,       WR_QPP | SECT_4K},

          {"N25Q128",    0x20ba18, 0x0,       64 * 1024,   256, RD_FULL,               WR_QPP},

          {"N25Q128A",         0x20bb18, 0x0,       64 * 1024,   256, RD_FULL,               WR_QPP},

          {"N25Q256",    0x20ba19, 0x0,       64 * 1024,   512, RD_FULL,       WR_QPP | SECT_4K},

          {"N25Q256A",         0x20bb19, 0x0,       64 * 1024,   512, RD_FULL,       WR_QPP | SECT_4K},

          {"N25Q512",    0x20ba20, 0x0,       64 * 1024,  1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},

          {"N25Q512A",         0x20bb20, 0x0,       64 * 1024,  1024, RD_FULL, WR_QPP | E_FSR | SECT_4K},

          {"N25Q1024",         0x20ba21, 0x0,       64 * 1024,  2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},

          {"N25Q1024A",        0x20bb21, 0x0,       64 * 1024,  2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},

          {"MT25QU02GC",       0x20bb22, 0x1044,    64 * 1024,  4096, RD_FULL, WR_QPP | E_FSR | SECT_4K},

    #endif

    This enhancement will be included in a future release of uboot-socfpga.

    Related Products

    This article applies to 2 products

    Intel® FPGA Configuration Devices
    Intel® Arria® 10 SX SoC FPGA

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