Article ID: 000086453 Content Type: Troubleshooting Last Reviewed: 06/22/2017

Why is Cyclone V HPS MPU clock setting incorrect?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In some cases, the HPS MPU clock frequency may be different from what the user has selected in Qsys.

    This problem is due to the bsp-editor incorrectly using the handoff information to create the Main PLL c0 divider settings to be used by the Preloader.

    The problem does not happen on all clocking configurations, but only for some configurations that require the main PLL c0 k divider to be changed from the default value of 1. The user can check if the configuration is affected by doing the following:

    o   Look into the handoff file called hps.xml for the  parameter called main_pll_c0_internal

    o   Look into the preloader/generated/pll_config.h for the following parameters: CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT, CONFIG_HPS_ALTERAGRP_MPUCLK

    o   If the following two divider values are equal, then the problem is not present:

    ·       value1 = (main_pll_c0_internal 1)

    ·       value2 = (CONFIG_HPS_ALTERAGRP_MPUCLK 1) x (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 1)

    Resolution

    This problem has been fixed in the Quartus® Prime Standard software version 16.1. 

    Related Products

    This article applies to 3 products

    Cyclone® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA

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