Article ID: 000086415 Content Type: Error Messages Last Reviewed: 05/07/2025

Error (suppressible): (vsim-3058) The width (83) of Verilog port 'av_st_din_data' does not match the array length (48) of its VHDL connection

Environment

    Intel® Quartus® Prime Pro Edition
    Clocked Video Output II (4K Ready) Intel® FPGA IP
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Description

Due to a problem in the Quartus® Prime software version 17.0 update 1 and earlier, you may see the error mentioned above while running VHDL VHDL-based simulation model for the Clock Video Output II IP core.

Resolution

This issue has no workaround; the user must install the Quartus® Prime Pro Edition Software version 20.2 to resolve it.

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This article applies to 1 products

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