Article ID: 000086406 Content Type: Troubleshooting Last Reviewed: 02/11/2013

Possible Timing Failures for LPDDR2 Designs on Cyclone V -7 Speed Grade Devices

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    This problem affects LPDDR2 products.

    LPDDR2 designs targeting Cyclone V -7 speed grade devices at 333 MHz may fail address and command timing analysis.

    Resolution

    The workaround for this issue is to operate the design at a lower frequency (such as 300 MHz), or use a -6 speed grade Cyclone V device.

    This issue will be fixed in a future release.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.