Article ID: 000086400 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Should the nCONFIG pin be pulled low when configuring a Stratix V ES device over JTAG using Quartus II Programmer, when the devices primary configuration scheme is AS, PS or FPP?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Stratix® V ES devices power up in secure mode, allowing only mandatory JTAG 1149.1 instructions after power-on reset (POR). If you use fast passive parallel (FPP), passive serial (PS), or active serial (AS) as your Stratix V ES primary configuration scheme, you will not be able to access the JTAG port after configuration completes.

If you wish to configure the device over JTAG using the Quartus® II programmer, Altera recommends pulling nCONFIG low before the device exits POR. This is required to prevent the device from configuring while the programmer executes the FACTORY instruction through the JTAG interface. You should pull nCONFIG high again after configuration is complete.

You should refer to Configuration, Design Security, and Remote System Upgrades in Stratix V Devices (PDF) for the minimum POR delay specification.

Related Products

This article applies to 4 products

Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Stratix® V E FPGA

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