Component generated in HLS do not cater the little endian/big endian conversion

The interface component generated by the HLS compiler is in little endian order(example interp_decim_filter) where some of the Altera® IP such as SGDMA is in big endian ordering. User may observe this when they import the component generated in the Platform Designer.

Currently the streaming interface's endian class is not created, where user need to manual handle the conversion for the time being. User could handle this in the component definition <component>_hw.tcl file.

This problem is fixed starting with the High Level Synthesis version 18.0. Parameter (firstSymbolInHighOrderBits) is added to handle the conversions on Streaming Interfaces.