Why do I see cache coherency problems between the HPS and FPGA on HPS designs using ACE-Lite interfaces in Intel Quartus Prime Pro version 20.4 and earlier?

Due to a problem in the Intel© Quartus© Prime Pro software version 20.4 and earlier, incorrect AXI signal values may be seen on transactions between
ARM® AMBA® AXI ACE-Lite Managers using the ARM AXI ACE-Lite protocol to connect to other logic in Platform designer,  such as HPS FPGA to SOC Bridges or Avalon® Agents.   This may be seen at run time as cache coherency errors. 

Patch 0.28 for the Intel® Quartus® Prime Pro software version 20.4 is available to fix this problem.   Download and install the patch from the
relevant link below, and re-compile your design.

quartus-20.4-0.28-linux.run

quartus-20.4-0.28-windows.exe

quartus-20.4-0.28-readme.txt

This problem is fixed in the Intel© Quartus© Prime Pro software version 21.1