Article ID: 000086360 Content Type: Troubleshooting Last Reviewed: 08/30/2017

Why I can’t see /sys/class/fpga-bridge/lwhps2fpag folder with my Linux in a A10 SoC kit?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You can run below commands to enable or disable bridges which are available in your SoC platform.

    echo 1 > /sys/class/fpga-bridge/fpga2hps/enable
    echo 1 > /sys/class/fpga-bridge/hps2fpga/enable
    echo 1 > /sys/class/fpga-bridge/lwhps2fpga/enable

     

     

     

    If you failed to find those folders, please check the DTS you are using to make sure below nodes are available:

     

    fpgabridge0: fpgabridge@0 {

                         compatible = "altr,socfpga-hps2fpga-bridge";    /* appended from boardinfo */

                         label = "hps2fpga"; /* appended from boardinfo */

                         reset-names = "hps2fpga";  /* appended from boardinfo */

                         clocks = <&l4_main_clk>;    /* appended from boardinfo */

                         resets = <&hps_0_rstmgr 96>;    /* appended from boardinfo */

                  }; //end fpgabridge@0 (fpgabridge0)

     

                  fpgabridge1: fpgabridge@1 {

                         compatible = "altr,socfpga-lwhps2fpga-bridge"; /* appended from boardinfo */

                         label = "lwhps2fpga";    /* appended from boardinfo */

                         reset-names = "lwhps2fpga";      /* appended from boardinfo */

                         clocks = <&l4_main_clk>;    /* appended from boardinfo */

                         resets = <&hps_0_rstmgr 97>;    /* appended from boardinfo */

                  }; //end fpgabridge@1 (fpgabridge1)

     

                  fpgabridge2: fpgabridge@2 {

                         compatible = "altr,socfpga-fpga2hps-bridge";    /* appended from boardinfo */

                         label = "fpga2hps"; /* appended from boardinfo */

                         reset-names = "fpga2hps";  /* appended from boardinfo */

                         clocks = <&l4_main_clk>;    /* appended from boardinfo */

                         resets = <&hps_0_rstmgr 98>;    /* appended from boardinfo */

                  }; //end fpgabridge@2 (fpgabridge2)

     

                  fpgabridge3: fpgabridge@3 {

                         compatible = "altr,socfpga-fpga2sdram-bridge"; /* appended from boardinfo */

                         label = "fpga2sdram";   /* appended from boardinfo */

                         read-ports-mask = <0x0000000f>;      /* appended from boardinfo */

                         write-ports-mask = <0x0000000f>;     /* appended from boardinfo */

                         cmd-ports-mask = <0x00000001>;     /* appended from boardinfo */

                  }; //end fpgabridge@3 (fpgabridge3)

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    Intel® Programmable Devices