Why does the FPGA configuration fail from Linux/U-Boot and cause the HPS to hang on Intel Stratix® 10 SX devices when I use the phase 1 and phase 2 bitstreams with RSU enabled that are generated from different Intel Quartus® Prime Pro?

Why does the FPGA configuration fail from Linux/U-Boot and cause the HPS to hang on Intel Stratix® 10 SX devices when I use the phase 1 and phase 2 bitstreams with RSU enabled that are generated from different Intel Quartus® Prime Pro Edition software versions?

Mixing the phase 1 and phase 2 bitstreams that are generated from different Quartus® Prime Pro Edition software versions is a non-supported use case.

No workaround/patch can be provided. Intel supported methodology is to generate the phase 1 and phase 2 bitstreams using the same Quartus® Prime Pro Edition software version (including patches if applicable).