Article ID: 000086350 Content Type: Error Messages Last Reviewed: 01/12/2018

Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_gen7_router_callbacks.cpp, Line: 349

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 17.1 Update 1 and earlier, you may see this internal error during placement of a Intel® Stratix® 10 design containing multiple clock domains.

    The internal error may occur when a design contains multiple asynchronous clock domains which have not been declared as being asynchronous in the Synopsys Design Constraints files (.sdc).

    Resolution

    To work around this problem, ensure that all asynchronous clock domains are declared as being asynchronous using the set_clock_groups command.

    For Example:
    set_clock_groups -asynchronous -group [get_clocks <clock A>] -group [get_clocks <clock B>]

     

    This problem is scheduled to be resolved in a future release of the Intel Quartus Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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