Article ID: 000086315 Content Type: Product Information & Documentation Last Reviewed: 01/08/2015

How do I decode the AXI ID fields from the HPS-FPGA bridges for Cyclone V and Arria V SoC devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The ARID, AWID, WID, RID, and BID signals indicate the master and routing for a particular memory access that is made by the HPS-FPGA bridges (either the HPS-to_FPGA bridge or the Lightweight HPS-to-FPGA bridge).

For Arria® V and Cyclone® V SoC devices, the AXI ID that is outputted from the L3 interconnect is a 12-bit vector made up of these fields:
ID[12]    : Interconnect ID, IID
ID[11:3] : Virtual ID, VID
ID[2:0]   : Slave Interconnect ID, SIID

The VID is received from the master which the transaction is received from, the IID and SIID are assigned by the L3 interconnect as shown:

Master IID (xxID[12]) SIID (xxID[2:0])
MPU 1b03b010
DMA1b0 3b001
DAP 1b03b100
FPGA2HPS 1b03b000
DMA1b0 3b001
EMAC01b13b001
EMAC11b13b010
USB01b13b011
NAND1b13b100
TMC1b13b000
SD/MMC1b13b101
USB11b13b110

The 8 bit VID is set by the master that sent the transaction to the L3 interconnect.

The VID for the MPU master is set according to the AMBA® Level 2 cache controller L2C-310 revision r3p0 Technical Reference Manual, available from the ARM® info center website http://infocenter.arm.com.

The VID for the FPGA2HPS master is from the 8-bit AXI ID inputs to the FPGA2HPS bridge.

The VID for the DMA master has bits 7:4 set to 0, and bits 3:0 set according to the ARM CoreLink DMA-330 revision r1p1 Technical Reference Manual.

The VID for the EMAC0 and EMAC1 masters is set to 8h00 for Rx DMA accesses and 8h01 for Tx DMA accesses.

The VID is always set to 0 for USB0, USB1, TMC, DAP, NAND and SDMMC masters.

This information will be included in a future version of the respective device handbooks.

Resolution

 

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA

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