Article ID: 000086309 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I see recovery timing violations within the ALTLVDS_RX megafunction in my design?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see recovery timing violations on the reset path from your user-coded reset register through the rx_cda_reset port of the ALTLVDS_RX megafunction to the following signals *altlvds_rx_component|*auto_generated|rx*bit_slip_reg

Address these paths by applying a set of set_multicycle_path assignments such as the ones below:

set_multicycle_path -from [get_keepers <name of source node>] \
    -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*bit_slip_reg}] \
    -setup -end 3 .
set_multicycle_path -from [get_keepers <name of source node>] \
    -to [get_keepers {*altlvds_rx_component|*auto_generated|rx*bit_slip_reg}] \
    -hold -end 2 .

The values of these assignments may vary depending on the relationship between the clock used for your external register and the rx_outclock port of the ALTLVDS_RX megafunction.

Altera recommends using the rx_outclock port of the ALTLVDS_RX megafunction to clock the external reset register to synchronize the reset to the correct domain.

Related Products

This article applies to 24 products

Cyclone® III FPGAs
Stratix® V GX FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Stratix® V GT FPGA
Cyclone® II FPGA
Stratix® V GS FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Cyclone® FPGAs
Stratix® III FPGAs
Stratix® IV GX FPGA
Arria® II GZ FPGA
Arria® II GX FPGA
Arria® GX FPGA
Stratix® IV GT FPGA
Stratix® V E FPGA
Stratix® FPGAs
HardCopy™ III ASIC Devices
HardCopy™ IV E ASIC Devices
Stratix® GX FPGA
HardCopy™ IV GX ASIC Devices
Cyclone® III LS FPGA
Stratix® IV E FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.