Article ID: 000086302 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Is there an issue with the location display of certain pins in Stratix IV and Arria II GX device IO pads in the Pads View and Chip Planner?

Environment

  • Quartus® II Subscription Edition
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    Description

    Yes, there is an issue with the location display of certain pins in Stratix® IV and Arria® II GX device IO pads in the Pads View and Chip Planner. Due to this issue the fitter may give you an error message during compilation such as:

    Error: Pad <pad number> of non-differential I/O pin <pin name> in pin location <pin number> is too close to pad <pad number> of differential I/O pin <pin name> in pin location <pin number> -- pads must be separated by a minimum of 1 LAB row(s). Use the Pad View of Pin Planner to debug.

    In this case, the error message pads location may not be in the same place as shown in Pads view or Chip Planner.

    To verify whether or not the assigned IO pads location are adjacent to each other, you can include the “Pad Group” column in Pin Planner table with all pins being listed. Every four IO pads on same IO_block have same “Pad Group” number. For example, “Pad Group” number 10 is adjacent to “Pad Group” numbers 9 and 11.

    The affected Quartus® II software versions for the Pads View problem are versions 9.1SP1 and earlier. The fix for Pad View is implemented in Quartus II software version 9.1SP2.

    The affected Quartus II software versions for the Chip Planner problem are versions 10.0 and earlier.

    Resolution The fix for Chip Planner is scheduled for a future release of the Quartus II software.

    Related Products

    This article applies to 3 products

    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Arria® II GX FPGA

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