SerialLite III Streaming IP Core with ECC Enabled Mode has Incorrect ECC Bits Assigned in tx_error Port

For Stratix V, Arria V GZ, and Arria 10 SerialLite III Streaming IP Core with ECC enabled mode, the ECC error status bits are incorrectly assigned in the tx_error port (tx_error[2:1]), where tx_error[1] is assigned with ECC fatal error, and tx_error[2] is assigned with ECC correctable error.

The correct assignment should be tx_error[1]: ECC correctable error.

There is no workaround for this issue.

This issue will be fixed in a future release.