PLL reconfiguration will fail if your parameter instruction signals are clocked by ALTPLL_RECONFIG scanclk to initiate the PLL reconfiguration. The ALTPLL_RECONFIG megafunction is latched at every rising edge of its input clock. The ALTPLL_RECONFIG will generate scanclk which has the same frequency as the input clock but there is some delay between the input clock and scanclk. If you clocked the parameter instruction signals using scanclk, these signals could have missed the first rising edge of the input clock and must wait until the next rising edge to get latched. If the parameter input signal is not long enough to get latched until the next rising edge, the ALTPLL_RECONFIG megafunction can not recognize these instructions and can lead to PLL reconfiguration failure. To avoid this failure, you can clock all of the parameter instruction signals with the ALTPLL_RECONFIG input clock, so that these signal will get latched at the first rising edge of the input clock.
For further information refer to Phase-Lock Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction (PDF).