Critical Issue
Description
When the rx_protocol_clk clock is used, the Quartus II Design Assistant reports the following error:
“Critical Warning: (High) Rule D103: Data bits are not
correctly synchronized when transferred between asynchronous clock
domains.”
This clock is not constrained in the SDC file.
Resolution
Add the following constraints into the SDC file:
set rx_protocol_clk_name "rx_protocol_clk[1]"
create_clock -name -period 13.468
-waveform {0.000 6.734} [get_ports ]