Article ID: 000086186 Content Type: Troubleshooting Last Reviewed: 05/23/2016

IntxAck_o of the Hard IP for PCI Express with Avalon-MM Interface Is Connected to 1'b0 for Cyclone V and Arria V Devices

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

IntxAck_o is active in the Legacy Interrupt Assertion and Legacy Interrupt Deassertion timing diagrams found in the Arria V and Cyclone V Avalon-MM Interface for PCIe Solutions User Guides. However, for Arria V and Cyclone V devices, IntxAck_o is not active.

Resolution

No workaround is necessary. IntxReq_i instructs the Hard IP for PCI Express to send an Assert_INTA message TLP. The deassertion of IntxReq_i instructs the Hard IP for PCI Express to send a Deassert_INTA message.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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