Article ID: 000086183 Content Type: Troubleshooting Last Reviewed: 12/06/2018

Why do I see PLL locking issues and data errors when I use the 100MHz FPGA input clock (fpga_clk_100) in the Intel® Stratix® 10 SoC Golden Hardware Reference Design (GHRD)?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The FPGA 100MHz clock fpga_clk_100 on PIN_AW10 is incorrectly defined as a LVDS clock in the Intel® Stratix® 10 SoC Golden Hardware Reference Design (GHRD)  version 18.1 and earlier.   This can cause unexpected behaviour in the design for logic clocked from this source.

    Resolution

    To resolve this issue,  edit the IO assignment for fpga_clk_100 from LVDS to 1.8V  (PIN_AW10) using the Assignment->Assignment Editor or Assignments->Pin Planner tools.

     

    Note:  If the design has been compiled the IO standard on the auto created LVDS complement signal fpga_clk_100(n)  must be set to 1.8V.  The auto created LVDS complement signal will then be removed automatically.

     

    This fix is scheduled to be included in a future version of the  Intel Stratix 10 SoC GHRD.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 SX SoC FPGA

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